- Austin, Texas, United States +1 more
- On-site
- Full-time · Associate
- 3+ years
Design and deliver high-performance analog layout for PMU and chip-level IPs.
Locations (2)
- Austin, Texas, United States
- Cupertino, California, United States
Responsibilities
- Deliver PDV clean layout
- Plan and schedule work with circuit design team
- Recognize failure-prone circuit and layout structures
- Run design verification tools on Mega-cell and chip level
- Interpret LVS, DRC and ERC reports
Requirements
- BS in relevant field
- Master's Degree preferred