Referso Jobs

Analog IC Design Engineer

Fairchild Imaging, Inc. · Posted Nov 9, 2026

Open

San Jose, California, United States
$120K–$160K per year
3–8 years

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Analog IC Design Engineer

Fairchild Imaging, Inc. · Posted Nov 9, 2026

Open

San Jose, California, United States
$120K–$160K per year
3–8 years

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Senior Physical Design Verification Engineer

Microsoft · Posted Nov 9, 2026

Open

Hillsboro, Oregon, United States
Senior
$120K–$235K per year
1+ years

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Lead physical design verification for Microsoft’s cloud infrastructure chips.

Compensation

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.

Responsibilities

Work closely with Physical Design Engineers on LVS, DRC, ERC, Antenna fixes
Drive full chip integration for physical design verification, signoff and Tape‑outs
Collaborate with clock, analog, integration teams on routing, power delivery, block integration
Work with 3pIP and 1pIP teams for SOC‑IP handshake
Work with CAD team, tool vendors, foundry and partners to develop and validate new tools, flows, runsets

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: BS/MS in Electrical or Computer Engineering
Nice to have: 5+ years of experience in semiconductor chip design/SOC physical design

Skills

Mentor Calibre

Mixed Signal Custom Layout - Temporary/Seasonal

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Open

Markham, Ontario, Canada
Temporary

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The full custom IC layout group is looking for a candidate to design the layout for digital and analog circuits based on schematics using industry leading CAD tools and cutting edge foundry technology.

Responsibilities

Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso.
Floorplan, route, and assemble lower-level cells into macros
Build black-box/abstract models and views consumed by other teams; contribute to tapeout collateral for custom blocks.
Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners.
Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality.

Requirements

Electrical Engineering Degree
Mechanical Engineering Degree
Electronics related Diploma
Nice to have: CMOS device/circuit theory
Nice to have: analog/digital layout best practices

Skills

Digital circuit layout Analog circuit layout Cadence Virtuoso DRC

Standard Cell Library Engineering Internship

Synopsys · Posted Oct 26, 2026

Open

Internship · Intern
0+ years

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Internship in standard cell library engineering, supporting build, validation, and release processes for semiconductor design flows.

Responsibilities

Support standard cell library build and integration flows
Integrate library views and deliverables across different process corners and configurations
Assist with maintaining and improving build scripts and automation infrastructure
Support library configuration management and release preparation
Perform functional, structural, and consistency checks on library deliverables

Requirements

Currently pursuing a degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field
Nice to have: Familiarity with AI tools and their application in engineering or automation

Skills

Basic understanding of CMOS technology and standard cell libraries Familiarity with EDA views and formats such as Liberty, LEF, GDSII, Verilog, and CDL/SPICE Basic knowledge of physical verification concepts, including DRC, LVS, ERC, and EM

Sr. Solutions Engineer

Fluence · Posted Nov 5, 2026

Open

Manila, Philippines
Senior
5+ years

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Senior Solutions Engineer/ Electrical Design Engineer providing technical analysis and engineering support for BESS generation projects.

Responsibilities

Work closely with Business Development team to deliver cost-effective proposals
Develop and maintain design standards, templates and tools for BESS Power System
Develop and maintain standard equipment specifications for bulk DC/AC Power System Components
Develop and maintain standardized protection and control scheme methodology for MV collection system and HV utility network coordination
Develop and implement system level positive sequence load flow model for utility scale grid interactive inverter systems

Requirements

BSEE

Skills

DC/AC Power Systems Design & Engineering Power System Protection Utility grid operation Load flow studies Transmission planning Feasibility studies

Senior Engineer II - Layout

Microchip · Posted Nov 5, 2026

Open

San Jose, California, United States
Senior
$70K–$205K per year
8–10 years

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Lead complex semiconductor layout design and verification for physical implementation and product outcomes.

Compensation

The annual base salary range for this position, which could be performed in the US, is $70,304-$205,000.*

Responsibilities

Define and execute highly complex layout architectures, floorplans, device structures, interconnect, power distribution, matching, shielding, extraction, and verification strategies within approved scope.
Integrate circuit, interface, technology, performance, power, area, reliability, manufacturability, design-rule, and schedule requirements.
Resolve critical layout, connectivity, parasitic, matching, coupling, electromigration, physical-verification, integration, or tapeout-readiness issues through structured root-cause leadership.
Evaluate evidence quality, uncertainty, risks, dependencies, waivers, and alternative approaches; communicate decision-ready recommendations.
Coordinate cross-functional technical decisions and layout closure within approved scope.

Requirements

Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field
Nice to have: Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field
Nice to have: experience with semiconductor custom, analog, digital, mixed-signal, memory, IO, pad, RF, ASIC, or SoC layout

Physical Design Engineer

Apple · Posted Nov 5, 2026

Open

Cupertino, California, United States +1 more
On-site
Full-time
$150K–$225K per year

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Contribute to all phases of the physical design of high-performance PHY design from RTL to delivery of final GDSII.

Locations (2)

Cupertino, California, United States
United States

Compensation

base pay range for this role is between $150,400 - $225,300/yr

Responsibilities

Generate block/chip level static timing constraints
Build full chip floor-plan including pin placement, partitions and power grid
Develop and validate high performance low power clock network guidelines
Perform block level place and route and close the design to meet timing, area and power constraints
Generate and implement ECOs to fix timing, noise and EM IR violations

Requirements

Master's degree or foreign equivalent in Electrical Engineering or related field

Skills

Layout/Mask Design

Apple · Posted Nov 5, 2026

Open

Austin, Texas, United States
On-site
2+ years

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Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.

Responsibilities

Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.
Work with Layout lead and circuit designers to review and analyze floorplans of complex circuits.
Responsible to run a complete set of layout design verification tools available and clean up megacells to match engineering specifications.
Work with Layout lead and circuit design team to plan, schedule work and negotiate layout tradeoffs as needed.
Interpret LVS, DRC and ERC report to find the fastest way to complete layouts.

Requirements

Bachelor's degree in Electrical Engineering

Skills

layout floor-planning standard cell planning hierarchical layout assembly RC delay electromigration self-heating

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