- Cupertino, California, United States
- On-site
- Full-time · Associate
- $187K–$225K per year
Build and set up emulation models for various SoC designs at the full-chip and block level using Verilog RTL.
Compensation
The base pay range for this role is between $187,069 - $225,300/yr
Responsibilities
- Build and set up emulation models for various SoC designs
- Write and modify Verilog RTL, C/C++ DPI transactors, SV Assertions and coverage
- Utilize scripting languages including Python, Perl, Makefile to maintain and create new flows
- Collaborate with CAD, design verification, Silicon validation, DFT and SW teams
- Debug and root-cause bugs using bus/signal monitors, waveform, logs, and tools
Requirements
- Master’s degree in Computer Engineering, Computer and Information Technology, or a related field