- Remote, United States
- Remote
- Full-time · Senior
- $200K–$300K per year
- 8+ years
As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation.
Compensation
The base salary range for this role is $200,000 – $300,000.
Responsibilities
- Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.
- Integrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.
- Work directly in RTL, synthesis, and DFT tool flows.
- Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.
- Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.
Requirements
- BS, MS, or PhD in Electrical Engineering or Computer Engineering
- Nice to have: High-performance AI accelerators
- Nice to have: GPUs
- Nice to have: CPUs
- Nice to have: Networking ASICs