- Hyderabad, Telangana, India
- Senior
- 5+ years
Senior IP Design engineer with extensive FPGA RTL design experience
Responsibilities
- Design FPGA RTL logic
- Verify logic and perform timing closure
- Debug hardware and validate designs
- Package soft IP and develop testbenches
Requirements
- BS/MS/PhD in Electronics or Computer Engineering
- Nice to have: Hardware validation and debug
- Nice to have: Soft IP packaging
- Nice to have: Example design
- Nice to have: Testbench development