DFT Engineer
Katalyst Healthcares & Life Sciences · Posted Nov 5, 2026
- San Jose, California, United States
- Mid
- 4+ years
Responsibilities
- Perform DFT and ATPG for SoC or ASIC designs
- Manage DFT fundamentals including controllability, observability, and scan-based testing
- Handle ATPG pattern generation, analysis, and debug
- Manage MBIST including memory test architectures and diagnostics
- Apply IO Test methodologies for interface and pin-level validation
Requirements
- B-Tech
- BE
- Electronics domain degree
- Nice to have: silicon bring-up
- Nice to have: production test support