Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis and sign off.
Be responsible for a comprehensive DFT plan and drive the implementation.
Work with DFT and cross functional teams
Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full-chip level
Design and implement power management, reset, and clocking solutions for RISC-V CPU and SoC IP.
Compensation
Base Pay Range
$205,740.00-$251,460.00
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Responsibilities
Work with the architecture team to understand and define power management requirements.
Architect, design and implement core clocking, reset and power management solutions.
Microarchitecture development and specification. Ensure that knowledge is shared via clear documentation and participation in a culture of collaborative design.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with a physical implementation team to implement and optimise physical design to meet frequency, area, power goals.
Requirements
BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.
Nice to have: AMBA Interconnect Protocols such as AXI, AHB, and APB
Nice to have: AMBA Low Power Protocol Interface including P-channel and Q-channel protocols
Nice to have: Scala/Chisel, Bluespec, or other language/DSL for expressing configurable hardware via software
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