Lead Foundry Interface Engineer responsible for collaborating with internal design teams and semiconductor foundries to enable chip development, tape out, debug and release for display and mixed signal products.
Responsibilities
Work closely with display product and chip design teams to enable chip development, tape out, debug and release.
Work closely with foundries on silicon process and product issues.
Manage & evaluate foundry deliverables (PDK documentation, LVS, DRM/DRC, Spice models and tech files) and drive improvements with foundry.
Participate in technology development, device engineering for next generation process technologies.
Assess device usage cases to ensure product reliability (safe-operating-area evaluation).
Requirements
Bachelor's degree
Nice to have: MS or PhD
Nice to have: deep knowledge of mixed signal technologies
Nice to have: supporting analog design
Nice to have: experience with significant digital content
Lead critical initiatives within the New Technology Bridge Device Integration team to optimize transistor performance and yield for 14nm derivative generation.
Responsibilities
Ensure targeting of transistor focused Electrical Test trends to Customer/Product Specifications and perform timely root cause study to shifts or abnormality.
Analyze process interactions to ET while also understanding ET data effect on Parametric Yield.
Own parametric yield, wafer acceptance electrical Test, model to hardware correlation management for one or more customer accounts/products.
Design, execute, and analyze experiments to optimize transistor performance/variation with end goal of meeting design requirements while improving parametric yield and ensuring a reliable and manufacturable product.
Drive Task Force Teams to solve systematic yield, performance, or reliability issues.
Requirements
Bachelor's of Science or Engineering (Electrical, Computer, Material Science, or related areas)
Senior engineer responsible for developing, qualifying, and delivering production-quality EM/IR reliability collateral and methodologies across advanced process technologies for Intel’s PDK Reliability Verification / EMIR team.
Locations (3)
Phoenix, Arizona, United States
Folsom, California, United States
Santa Clara, California, United States
Compensation
Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD
Responsibilities
Develop, qualify, and maintain PDK EMIR collateral, documentation, and technology-specific configurations.
Own or contribute to PDK and Reliability Technology Kit (RTK) development, qualification, QA, and release readiness.
Develop and maintain test structures and automated validation for EM/IR collateral, including validation and cross-tool correlation.
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