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1–2 jobs· newest first

ASICS Design Engineer, SeniorNew
Qualcomm · Hsinchu City, Taiwan
On-site · Senior
ASICS Design Engineer, StaffNew
Qualcomm · Hsinchu City, Taiwan
On-site · Full-time · Staff

+10K new in the last hour

ASICS Design Engineer, Senior

Qualcomm · Posted Nov 9, 2026

Hsinchu City, Taiwan
On-site
Senior
2–10 years

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AI

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Lead ASIC design and delivery for Ethernet switch subsystems, driving architecture-aligned implementation, optimization, and integration.

Responsibilities

Implement RTL design, synthesis, and timing closure for networking datapath/control logic
Participate in SoC integration with focus on Ethernet switch subsystems
Lead design and delivery of key subsystems in Ethernet switch ASICs
Own micro-architecture and RTL design of networking blocks
Drive subsystem integration, performance tuning, and power optimization

Requirements

Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field

Skills

ASIC design RTL coding verification synthesis timing closure physical design flow ASIC FE design flow Ethernet switching concepts L2/L3 forwarding bridging routing packet processing pipelines QoS buffer management protocols (Ethernet, VLAN, TCP/IP, tunneling)AXI/NoC PCIe high-speed interfaces debugging system-level problem solving scripting (C/C++, Tcl, Perl)

See full job description

ASICS Design Engineer, Staff

Qualcomm · Posted Nov 9, 2026

Hsinchu City, Taiwan
On-site
Full-time · Staff
2–10 years

Apply with RefersoAI Apply on careers page

Implement RTL design, synthesis, and timing closure for networking datapath/control logic for Ethernet switch ASICs.

Responsibilities

Implement RTL design, synthesis, and timing closure for networking datapath/control logic.
Participate in SoC integration with focus on Ethernet switch subsystems.
Lead design and delivery of key subsystems in Ethernet switch ASICs, driving architecture-aligned implementation and optimization.
Own micro-architecture and RTL design of networking blocks (e.g., forwarding engine, parser, traffic manager).
Drive subsystem integration, performance tuning, and power optimization.

Requirements

MS/BS in EE (MS preferred)
Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field
Nice to have: merchant silicon

Skills

ASIC design logic design RTL coding verification synthesis

physical design

Ethernet switching

L2/L3 forwarding

Packet processing pipelines

See full job description