Lead ASIC implementation with focus on Design-for-Test within Cisco’s Silicon One team, driving DFT requirements, quality processes, and post-silicon validation.
Locations (2)
Vancouver, British Columbia, Canada
United States
Compensation
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Lead ASIC implementation and DFT design
Collaborate with front-end RTL and backend physical design teams
Drive DFT requirements early in design cycle
Craft next-generation networking chips
Lead DFT and quality process through implementation flow
Requirements
Bachelor’s degree in Electrical or Computer engineering
Master’s degree in Electrical Engineering or Computer Engineering
PhD in Electrical Engineering or Computer Engineering
Architect and drive complex pre-silicon verification, including SoC security verification, for Microsoft’s AI accelerators from block to chip and system level through post-silicon validation.
Locations (3)
Redmond, Washington, United States
San Francisco, California, United States
New York City, New York, United States
Compensation
Silicon Engineering IC6 - The typical base pay range for this role across the U.S. is USD $165,600 - $296,400 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year.
Responsibilities
Create complex verification environments and tests, driving pre-silicon functional verification at the block, chip, and system level, reference modeling, and post-silicon validation.
Interact with architects and design engineers to create verification plans covering strategy, test environments and tests, and verification requirements for IP, subsystem, and SoC level verification, then create and drive test plans and test development to provide complete feature coverage.
Defining SoC security architecture and threat models, including secure boot, root of trust, identity, isolation, privilege, debug, lifecycle, and recovery.
Develop verification components such as scoreboards, sequences, constraints, assertions, and functional coverage, along with Makefiles and scripts for scalable and efficient verification.
Develop and implement technical solutions to complex quality and design challenges, and triage and debug testbench, simulation, and emulation failures.
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: CPU, graphics, or NPU security architecture
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