We are looking for a Cyber-Physical Systems Reverse Engineer to support a new project researching and developing novel capabilities for maritime cybersecurity.
Compensation
Pay Range $107,900.00 - $195,050.00
Responsibilities
Develop, integrate, and debug embedded firmware for real-time and resource-constrained systems, including RTOS-based applications, device drivers, hardware interfaces, and low-level system software
Design and implement simulation, emulation, and automated test environments for embedded and cyber-physical systems, including tools for exploring system behavior, reproducing observed effects, and exercising hardware and firmware
Analyze and reverse engineer embedded devices, firmware, communications protocols, sensors, and other system components to understand both intended functionality and real-world behavior
Develop production-quality C/C++ and Python software to automate testing, instrumentation, experimentation, and analysis, including integration with laboratory hardware and software-based analysis tools
Conduct hands-on laboratory testing using embedded debugging tools and analog/digital instrumentation; critically analyze, document, and communicate technical findings
Requirements
Nice to have: Reverse engineering embedded devices and firmware using tools such as Ghidra, Binary Ninja, IDA Pro
Nice to have: Program analysis and vulnerability research techniques (fuzzing, symbolic execution, static/dynamic analysis, binary exploitation)
Own the technical direction of the platforms and the virtualization stack for EC2 instance families. Set multi-year technical direction, architectural decisions, and grow engineers across all levels.
Locations (2)
Berlin, Berlin, Germany
Seattle, Washington, United States
Responsibilities
Own part of the technical strategy for EC2 Core Compute and set multi-year direction with specific yearly production deliverables.
Define how a new processor generation from Intel, AMD or AWS Graviton becomes an EC2 platform: hardware specification review, firmware and hypervisor enablement, qualification, launch and fleet support.
Influence the architecture of the Nitro System as a whole, from the Linux kernel the hypervisor is built on to the firmware and services around it.
Set the engineering standard for how the organization builds systems software.
Improve the way the organization operates, maintains, monitors and automates its software and services.
Lead the development, integration, and productization of high-performance interface solutions for FPGA products.
Responsibilities
Lead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related interface subsystems.
Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.
Drive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
Work with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.
Drive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
Emulation experience on any/all available platforms (Palladium, Protium, Veloce, or Zebu, EP) including design bringup, build flow, debug, performance and throughput tuning.
Experience with Verilog, VHDL design Knowledge
Experience with C/C++, DPI and System Verilog add on.
Experience writing scripts using any languages (Perl, Python, Makefile )
Experience with waveform debug tools, Verdi/SimVision.
Talented engineer to join the CPU design team to drive performance verification and correlation between RTL and the performance model for a CPU based on RISC-V ISA.
Locations (2)
Austin, Texas, United States
Santa Clara, California, United States
Compensation
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets.
Responsibilities
Join a team driving improvements in CPU microarchitecture, verify performance and correlate RTL against the performance model.
Collaborate closely with RTL engineers and core architects to meet performance goals, debug miscorrelation and verify performance features.
Draft performance testplans and develop targeted microbenchmarks to exercise performance features and expose bottlenecks.
Enhance tools and methodologies for performance analysis and correlation to improve development efficiency.
Use innovative techniques to optimize power, performance, and area while driving performance experiments and evaluating results.
Validate power management architectures and features for Intel's next-generation SoC products, develop validation strategies, execute test plans, and debug complex design issues.
Locations (3)
Folsom, California, United States
Santa Clara, California, United States
Hillsboro, Oregon, United States
Compensation
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD
Responsibilities
Develop and execute comprehensive validation plans
Design, develop, and maintain validation environments and automated test content
Validate power management features such as DVFS, power gating, clock gating, low‑power states, reset flows, thermal management, and telemetry
Develop validation content using SystemVerilog, UVM, simulation, and emulation platforms
Serve as the primary technical resource for the verification team, leading end-to-end verification of IPs and their integration using best-in-class methodologies.
Responsibilities
Serve as the primary technical resource for the verification team, providing expert guidance.
Act as the central liaison to other verification and methodology teams at Infineon to coordinate strategies and resolve issues centrally
Lead and execute end-to-end verification of IPs and their integration using best-in-class methodologies (e.g., formal verification, AI-assisted testing)
Lead and review the third-party’s verification methodology and execution, from planning through implementation to final sign-off
Drive vendor accountability to close gaps and meet milestone targets
Requirements
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field
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