- Hyderabad, Telangana, India
- On-site
- Full-time · Senior
- 5–7 years
Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis etc in ASIC PNR Flow, and full chip implementation of complex SoCs (RTL-to-GDSII).
Responsibilities
- Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis etc in ASIC PNR Flow
- Execute the block level place and route assignments from Netlist through GDS flow
- Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed
- Close STA timing across all corners and modes for blocks and should be able to generate ECO independently
- Work with design teams for closing CTS, IO timing, DFT timing
Requirements
- 4 year degree