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1–2 jobs· newest first

Senior IP/Sub System Design Verification Engineer, Google Cloud
Google · Bengaluru, India
On-site · Full-time · Senior
Sr Staff QA/Test Eng(RTL, FPGA backend tools)
Lattice Semiconductor · Pune, India
Senior

+10K new in the last hour

Senior IP/Sub System Design Verification Engineer, Google Cloud

Google · Posted Nov 12, 2026

Bengaluru, Karnataka, India
On-site
Full-time · Senior
8+ years

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Own the full verification life-cycle from verification planning and test execution, emphasizing AI/ML performance and accuracy goals on TPU hardware.

Responsibilities

Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology.
Verify designs with SystemVerilog Assertions and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
Nice to have: Artificial Intelligence/Machine Learning (AI/ML) accelerators
Nice to have: vector processing units
Nice to have: industry-standard simulators

Skills

SystemVerilog Specman/E RTL verification IP component verification packet processing bandwidth management congestion control SystemVerilog Assertions formal tools

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Sr Staff QA/Test Eng(RTL, FPGA backend tools)

Lattice Semiconductor · Posted Aug 31, 2026

Pune, Maharashtra, India
Senior
12+ years

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Senior QA/Test Engineer focused on FPGA backend tools and RTL verification.

Responsibilities

Create and maintain test suites for Radiant backend tools
Execute test plans for new features
Analyze regression failures and report to stakeholders
Drive issue closure
Automate test activities using AI offerings

Requirements

BS/MS in Electrical, Electronics or Computer Science or Computer Engineering
Nice to have: Python
Nice to have: Perl
Nice to have: TCL
Nice to have: PCIe

Skills

FPGA backend tools Radiant Vivado Synthesis Synplify Map Place and Route Bitgen RTL verification

Debugging in simulation and hardware

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