Own the full verification life-cycle from verification planning and test execution, emphasizing AI/ML performance and accuracy goals on TPU hardware.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology.
Verify designs with SystemVerilog Assertions and industry leading formal tools.
Identify and write all types of coverage measures for stimulus and corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science
Nice to have: Artificial Intelligence/Machine Learning (AI/ML) accelerators
Develop custom silicon solutions powering Google's direct-to-consumer products, contributing to the innovation behind products loved by millions worldwide.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology
Verify designs with SystemVerilog Assertions and industry leading formal tools
Identify and write all types of coverage measures for stimulus and corner-cases
Debug tests with design engineers to deliver functionally correct design blocks
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Locations (2)
Haifa, Haifa District, Israel
Tel Aviv, Tel Aviv, Israel
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Senior IP/Sub System Design Verification Engineer, Google CloudGoogle · Bengaluru, India