- Manila, Philippines
- Senior
- 6–10 years
Lead design verification for programmable logic solutions, developing comprehensive verification plans, testbenches, and regression environments.
Responsibilities
- Develop comprehensive verification plans and metrics
- Verify design blocks, subsystems and full chip using assertion-based, formal, directed and randomized tests
- Develop System Verilog and C based testbenches in UVM environment
- Design and develop testbench components such as Universal Verification Components, BFMs and verification tools
- Define and design verification regression environment
Requirements
- Bachelor's or Masters Degree in Computer Science
- Bachelor's or Masters Degree in Computer Engineering
- Bachelor's or Masters Degree in Electronics
- Bachelor's or Masters Degree in Electrical Engineering