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Lead Design for Test (DFT) engineering responsibilities including MBIST, EDT, OCC, SSN Insertion, Scan insertion, ATPG, VCS simulation, timing closure, DFT DRC debug and simulation debug.

Responsibilities

Lead DFT engineering activities
Manage MBIST, EDT, OCC, SSN Insertion, Scan insertion, ATPG
Perform VCS simulation
Ensure timing closure for DFT logic
Debug DFT DRC and simulation

Skills

MBIST EDT OCC SSN Insertion Scan insertion ATPG VCS timing closure DFT DRC debug Simulation debug

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DFT Engineer

Quest Global · Posted Nov 5, 2026

Open

Vietnam
Mid
4–6 years

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Experienced DFT Engineer with 4 to 6 years of experience specializing in Tessent expertise, simulation, and timing closure debug for DFT logic.

Responsibilities

Utilize Tessent expertise for MBIST, EDT, OCC, SSN Insertion, Scan insertion, and ATPG
Perform simulation using VCS
Handle timing closure for DFT logic
Execute DFT DRC debug and Simulation debug

Skills

DFT Tessent MBIST EDT OCC SSN Insertion Scan insertion ATPG VCS timing closure DFT DRC debug Simulation debug

Simulation debug jobs

Responsibilities

Skills

Responsibilities

Skills

Responsibilities

Skills

Responsibilities

Skills