- Palo Alto, California, United States
- Full-time · Mid
- $237K–$296K per year
Seeking an RTL Design Engineer to join the Neural Network Engine (NNE) design team to define microarchitecture and deliver production-quality RTL for compute, memory, datapath, and control blocks in an advanced SoC environment.
The listed base salary range for this role is $237,000 - $296,000 for San Francisco Area based applicants.
Design and implement digital blocks in Verilog/SystemVerilog, translating functional requirements into robust, synthesizable RTL and contribute to microarchitecture definition.
The expected annual pay range for this position is €37,000–€50,000. Please note that the final offer will depend on factors such as geographic location, relevant experience, and the candidate’s skill set. This role is also eligible for a bonus.