Lead verification of pixel pipe subsystems and develop complex SystemVerilog and UVM test benches for high-performance computing devices.
Locations (2)
San Jose, California, United States
Austin, Texas, United States
Compensation
base pay range for this role is between $216,091.00-$251,760.00
Responsibilities
Lead the verification of pixel pipe subsystems, including scalar/vector ALUs, register files, and instruction issue logic, ensuring functional correctness and performance targets.
Develop and maintain complex SystemVerilog and UVM test benches to simulate and validate shader pipeline behavior under various workloads.
Drive creation of detailed verification plans, leveraging architectural specifications microarchitecture design docs, and cross-functional input.
Collaborate closely with RTL designers, compiler teams, and architecture to identify corner cases, debug failures, and improve design quality.
Utilize coverage-driven verification methodologies to achieve functional and code coverage goals; analyze and close gaps proactively.
Requirements
Master’s degree or foreign equivalent in Computer Science, Computer Engineering, Electronics Engineering, Electrical Engineering, or a closely related field
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