Bachelor/ Master Thesis - Implementation of a Latch-Based Register File for RISC-V Cores (f/m/div)
Infineon · Posted Oct 29, 2026
- Munich, Bavaria, Germany
- On-site
- Internship · Intern
Bachelor or Master thesis focused on the implementation of latch-based register files for RISC-V cores.
Responsibilities
- Get familiar with Infineon’s code generation framework, RISC-V processor architectures, and register-file implementations
- Investigate latch-based storage architectures and clocking schemes for processor register files
- Develop and implement a configurable latch-based register-file solution
- Evaluate implementation options with respect to timing, area, power, and robustness
- Analyze DFT aspects and compare latch-based and flip-flop based approaches
Requirements
- Bachelor's or master's student in Computer Science
- Electrical Engineering
- Nice to have: German
- Nice to have: processor microarchitecture
- Nice to have: RISC-V