- Austin, Texas, United States
- Hybrid
- Full-time · Senior
- $200K–$350K per year
- 8+ years
As a Senior ASIC Design Verification Engineer, you will play a critical role in ensuring the functional correctness and performance of our AI inference ASICs. You will be responsible for developing and executing advanced verification methodologies, working closely with design, architecture, and software teams to validate our silicon solutions.
Compensation
The base salary range for this role is $200,000 – $350,000.
Responsibilities
- Develop and execute verification strategies for AI inference ASICs
- Define and implement comprehensive test plans and verification methodologies
- Lead the development of verification environments using SystemVerilog UVM
- Create and maintain simulation testbenches, directed and constrained-random tests
- Collaborate with design and architecture teams to ensure functional coverage and closure
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
- Advanced degree in Electrical or Computer Engineering or related field
- Nice to have: hardware-software co-verification
- Nice to have: formal verification techniques
- Nice to have: post-silicon validation and bring-up methodologies