- Noida, Uttar Pradesh, India
- Full-time · Senior
- 4+ years
Lead design verification for ASIC and embedded IPs, creating UVM-based test benches and verification methodologies.
Responsibilities
- Create state‑of‑the‑art UVM test benches and methodologies
- Define test plans, tests and verification infrastructure for modules, IPs and sub‑systems
- Build efficient and reusable bus functional models, monitors, checkers and scoreboards
- Implement functional coverage and own verification closure
- Work with architects and design teams to ensure verification completeness
Requirements
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
- Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
- PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field
- Nice to have: Power Aware Verification