- San Jose, California, United States
- Full-time · Entry
An ASIC Design for Test Engineer role focused on Design-for-Test (DFT) within the Silicon One team creating hardware platforms.
Compensation
Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, and/or training.
Responsibilities
- Implement the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of the designs.
- Create and enhance automation scripts to improve implementation robustness and efficiency.
- Work closely with the Design, Design Verification, and Physical Design teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
- Collaborate with team members to validate test timing and logic equivalency of designs using SystemVerilog.
- Utilize ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.
Requirements
- Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months)
- Nice to have: SystemVerilog
- Nice to have: logic equivalency checking
- Nice to have: test-timing validation
- Nice to have: VLSI circuit physical behaviors