- Sunnyvale, California, United States
- Contract · Mid
Develop and execute verification environments for complex semiconductor designs using SystemVerilog and UVM.
Responsibilities
- Develop and maintain reusable UVM-based verification environments
- Create and implement test plans, test scenarios, and verification strategies
- Develop constrained-random and directed test cases using SystemVerilog
- Build and maintain UVM components, including agents, drivers, monitors, sequencers, and scoreboards
- Develop assertions using SystemVerilog Assertions (SVA)