Verification tools (QuestaSim/UVM) jobs

Advanced ASIC FPGA Engineer

General Dynamics Missions System International · Posted Nov 11, 2026

Open

Scottsdale, Arizona, United States
Hybrid
Full-time · Senior
$123K–$136K per year

Advanced ASIC FPGA Engineer

General Dynamics Missions System International · Posted Nov 11, 2026

Open

Scottsdale, Arizona, United States
Hybrid
Full-time · Senior
$123K–$136K per year

Digital Engineering and BIM Manager (M2)

Mace · Posted Nov 11, 2026

Open

Cairo, Cairo, Egypt
On-site

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Lead and manage BIM and information management functions for a large mixed‑use development in Egypt, ensuring compliance with ISO 19650 and related standards.

Responsibilities

Support delivery teams throughout the project lifecycle
Communicate effectively with clients, project teams and key stakeholders
Delegate tasks effectively and monitor successful delivery
Apply ISO 19650 requirements and relevant client information management standards
Develop Information Requirements, including OIR, AIR, PIR and EIR, in line with ISO 19650 and maintain the BIM Execution Plan (BEP)

Requirements

Level 6 qualification or equivalent in a relevant discipline

Skills

ISO 19650 BS 1192 Common Data Environments (CDE)IFC COBie Autodesk desktop products databases

Digital Engineering and BIM Manager (M2)

Mace · Posted Nov 11, 2026

Open

Cairo, Cairo, Egypt
On-site

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Lead and manage BIM and information management functions for a mixed-use development project in Egypt, ensuring compliance with ISO 19650 and related standards.

Responsibilities

Support delivery teams throughout the project lifecycle
Communicate effectively with clients, project teams and key stakeholders
Delegate tasks effectively and monitor successful delivery
Apply ISO 19650 requirements and relevant client information management standards
Develop Information Requirements, including OIR, AIR, PIR and EIR, in line with ISO 19650 and maintain the BIM Execution Plan (BEP)

Requirements

Level 6 qualification or equivalent in a relevant discipline

Skills

ISO 19650 BS 1192 Common Data Environments (CDE)IFC COBie Autodesk desktop products databases

Tech Lead - Robot Safety and Security

Bosch Group · Posted Nov 11, 2026

Open

Renningen, Baden-Württemberg, Germany

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Lead architecture and implementation of safety and security runtime software for industrial robots, overseeing verification, formal methods, and safety assurance.

Responsibilities

Own runtime and assurance architecture
Define verification strategy and evidence
Lead technical reviews of embedded implementation
Implement critical embedded runtimes and verification components
Guide sensing integration and hardware-in-the-loop testing

Requirements

Bachelor’s or Master’s degree in Computer Science
Robotics
Electrical Engineering
Control Engineering

Skills

C/C++real-time behavior sensing interfaces diagnostics failure handling safety engineering formal verification model checking

Mask Layout Design Lead

Qualcomm · Posted Nov 10, 2026

Open

Markham, Ontario, Canada
On-site
$46–$68
4+ years

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Lead mask layout design and team management for complex semiconductor projects.

Compensation

$45.58 - $68.36

Responsibilities

Leads team to read and develop highly complex project requirements and specifications
Defines and builds macro level layouts and floorplans
Develops and communicates guidelines, processes, design rule manuals, and checklists
Manages testing and validation of top-level designs using layout and verification tools
Provides guidance on gathering information and conducts advanced analyses and sign-off

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field
High School diploma or equivalent
Nice to have: Master's degree in Technology, Electrical Engineering, Electronic Engineering
Nice to have: 6+ years of experience designing custom layouts in a specific relevant technology

Skills

layout design verification tools cadence

Senior Analog Design Engineer

Renesas Electronics · Posted Nov 10, 2026

Open

Bingen, Baden-Wurttemberg, Germany
Senior
5+ years

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Design and optimize high-performance analog and mixed-signal ICs for automotive and industrial applications, including transistor-level design, simulation, silicon validation, and product qualification.

Responsibilities

Design and optimize analog and mixed-signal circuit blocks such as amplifiers, voltage references, regulators, data converters, and sensor interfaces.
Perform transistor-level design, simulation, and verification across process, voltage, temperature, and reliability conditions.
Drive silicon bring-up, characterization, debugging, and root-cause analysis through technically sound closure.
Contribute to product robustness, yield improvement, and long-term reliability.
Collaborate closely with Layout, Verification, Product, Test, and System Engineering teams.

Requirements

Bachelor's in Electrical Engineering, Microelectronics, Physics, or a related field
Master's in Electrical Engineering, Microelectronics, Physics, or a related field

Skills

Analog and mixed-signal IC design Transistor-level design Circuit simulation Verification

Intellectual Property and Product Compliance Specialist

allegrospz · Posted Nov 9, 2026

Open

Praha, Czech Republic

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Specialist responsible for acquiring and maintaining systematic knowledge of prohibited and regulated goods under local and international legal regulations and Allegro's Terms of Service, leading internal training and external workshops, using verification tools, monitoring and verifying offers and products, applying sanctions, and participating in cross-functional teams.

Responsibilities

Acquire and maintain systematic knowledge of prohibited and regulated goods under local and international legal regulations and Allegro's Terms of Service
Lead internal training for Allegro employees and external workshops for merchants
Utilize verification tools to check quality of offers and products
Effectively monitor and verify offers and products
Apply sanctions and measures in accordance with Allegro's Terms of Service

Skills

Intellectual Property law E-commerce regulations Counterfeit issues on online marketplaces Verification tools Decision making on sanctions

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Senior Mask Layout Design Engineer

NVIDIA · Posted Nov 7, 2026

Open

Hsinchu, Taiwan, Taiwan
Senior
5+ years

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Senior Mask Layout Design Engineer

Responsibilities

Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD structures designs in groundbreaking sub-micron CMOS technologies using Cadence tools.
Work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Take part in floor planning, custom layout and verifying against design rules and schematics.

Requirements

BSEE or equivalent

Skills

Mask and Layout Design analog circuit layout submicron CMOS technologies Cadence custom circuit design tools virtuoso verification tools Dracula Hercules

Advanced ASIC FPGA Engineer

Advanced ASIC FPGA Engineer

Compensation

Responsibilities

Requirements

Skills

Benefits

Digital Engineering and BIM Manager (M2)

Responsibilities

Requirements

Skills

Digital Engineering and BIM Manager (M2)

Responsibilities

Requirements

Skills

Tech Lead - Robot Safety and Security

Responsibilities

Requirements

Skills

Mask Layout Design Lead

Compensation

Responsibilities

Requirements

Skills

Senior Analog Design Engineer

Responsibilities

Requirements

Skills

Intellectual Property and Product Compliance Specialist

Responsibilities

Skills

Senior Mask Layout Design Engineer

Responsibilities

Requirements

Skills

Benefits