- Santa Clara, California, United States
- Senior
- $168K–$311K per year
- 6+ years
Design mixed-signal blocks for NVIDIA’s high-speed I/O SerDes group, contributing to NVLINK and other high-speed protocols.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 168,000 USD – 264,500 USD for Level 4; and 196,000 USD – 310,500 USD for Level 5.
Responsibilities
- Work with analog designers to create accurate SystemVerilog model of analog components such as closed-loop PLL, Rx CTLE, SAR ADC and optics components.
- Collaborate with system architects and digital designers to define and verify system architecture specifications and refine adaptation algorithms.
- Streamline workflows with scripts to increase efficiency and enable reusability.
- Participate in silicon bringup, build scripts for debug, QA, characterization and ATE.
Requirements
- B.S. or MS degree in Electrical Engineering or equivalent experience
- Nice to have: FPGA emulation