Lead SRAM design engineer responsible for architecture, circuit design, verification, and silicon bring-up of embedded memory IP
Compensation
$153,000.00 - $267,000.00 a year
Responsibilities
Design and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.
Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.
Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
Own transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation and waveform/debug reviews.
Drive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.
Requirements
BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field
Lead SRAM design engineer responsible for developing high-performance, low-power embedded memory IP and testchip content across the full memory-development lifecycle.
Compensation
$153,000.00 - $267,000.00 a year
Responsibilities
Design and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.
Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.
Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
Own transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation and waveform/debug reviews.
Drive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.
Requirements
BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field
