Setting up and supporting CAD flows, EDA tools, and foundry PDKs with a focus on analog/mixed-signal (AMS) design and custom layout, including automation and agentic AI integration.
Compensation
Pay range and Other Compensation & Benefits: $90,100.00 - $135,100.00
Responsibilities
Build and maintain agentic AI skills for AMS and custom layout
Help AMS design and layout teams adopt agentic AI through documentation, training and demos
Set up and support the CAD design environment and flows for analog and layout design teams
Support design flows from EDA vendors like Cadence & Synopsys
Install, set up and track foundry PDKs
Requirements
Bachelor's degree in Science, Engineering, or related field
Bachelor's degree in electrical engineering, computer engineering, computer science or a related field
Nice to have: Cadence SKILL programming
Nice to have: Synopsys Custom Compiler TCL/Python APIs
The Analog IC Design Engineer is responsible for the design and development of analog, mixed-signal IC circuit blocks from initial specification and architecture to final, post-silicon verification to ensure specifications are met.
Responsibilities
Analog, mixed-signal circuit design and simulation.
Work with mask designers to deliver physical design.
Integration of analog/mixed-signal blocks into large, complex, digital chips.
Define bench-level test plans for post-silicon characterization.
Post-silicon measurements, characterization, and debug.
The student will support the CMOS+X project by developing and refining an AI-assisted framework for discovering new and better-performing circuits using CaDRO for device sizing and SteerGenSE for circuit structure exploration.
Responsibilities
Implement and evaluate search algorithms
Improve circuit-generation models
Develop robust simulation testbenches
Benchmark candidate designs using Spectre and foundry device models
Work on cryogenic readout and control circuits, including low-dropout regulators, voltage-controlled oscillators, and switching regulators
Requirements
Currently enrolled in undergraduate or graduate studies at an accredited institution
Graduated from an accredited institution within the past 3 months
Actively enrolled in a graduate program at an accredited institution
Lead full-chip electrical specifications and mixed-signal design for Cisco's silicon photonics driver integrated circuits supporting 100G/200G/400G per Lambda solutions.
Responsibilities
Provide technical leadership in analog/mixed-signal design for Cisco's next generation silicon photonics driver integrated circuits
Lead full-chip electrical specifications, circuit design, and verification test plans from concept through production
Author mixed-signal datapath designs including photonics modulator drivers, serializers, PLLs, TIAs and control circuits
Debug complex silicon and system-level issues during bring-up and lab validation phases
Mentor and guide analog, digital, and validation engineers
Requirements
Bachelor's degree in Electrical Engineering or related field
Master's degree in Electrical Engineering or related field
PhD in Electrical Engineering or related field
Nice to have: 10-15 years of hands-on analog/mixed signal circuit design experience
Lead SRAM design engineer responsible for architecture, circuit design, verification, and silicon bring-up of embedded memory IP
Compensation
$153,000.00 - $267,000.00 a year
Responsibilities
Design and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.
Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.
Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
Own transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation and waveform/debug reviews.
Drive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.
Requirements
BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field
Design and simulation of advanced analog and mixed‑signal integrated circuits for high‑speed SerDes solutions.
Locations (2)
Cork, Munster, Ireland
Dublin, Leinster, Ireland
Responsibilities
Learn how system requirements are translated into analog and mixed‑signal circuit designs.
Support the design, simulation and optimization of transistor‑level circuits.
Work with analog building blocks such as amplifiers, bias circuits, voltage/current references, data converters, clocking circuits and high‑speed interfaces.
Run simulations across different operating conditions and analyse key performance metrics such as gain, bandwidth, noise, power, jitter and stability.
Gain exposure to custom IC layout, including matching, placement, routing and parasitic effects.
Lead SRAM design engineer responsible for developing high-performance, low-power embedded memory IP and testchip content across the full memory-development lifecycle.
Compensation
$153,000.00 - $267,000.00 a year
Responsibilities
Design and optimize custom SRAM, register-file, and embedded-memory circuits from architecture through schematic, layout support, characterization, and release.
Develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic, clocking, redundancy hooks, and read/write datapaths.
Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions.
Own transistor-level simulation and signoff using HSPICE, Spectre, FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation and waveform/debug reviews.
Drive SRAM PPA optimization through circuit sizing, architecture selection, banking and muxing decisions, assist techniques, bias strategies, retention modes, and critical-path analysis.
Requirements
BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field
Lead chip development from architecture to production, design analog and mixed-signal circuits in CMOS or BiCMOS, and guide block designers and layout team.
Compensation
At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent. In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.
Responsibilities
Lead development of analog mixed-signal IC and own the top level
Supervise and review block designer work and hold design review
Work with cross-functional team to architect the chip for DFT
Support cross-functional team for bench validation, qualification and final test development
Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes
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