Lead the product engineering organization for Navitas' SiC and GaN power device platforms, owning the full product lifecycle execution.
Responsibilities
Lead all SiC and GaN product engineering activities, overseeing the process from initial silicon development through qualification, production release, and ongoing sustaining support.
Lead and coordinate SiC and GaN product development, collaborating with Business Units, Technology Development, Foundry Device Engineering, OSATs, Test Engineering, Quality, Operations, and PMO.
Develop and implement CP, FT, and QC test programs with Test Engineering team, and oversee the electrical characterization of SiC and GaN products throughout their product lifecycle.
Oversee the creation and release of SiC and GaN datasheets and all associated documentation.
Work with reliability engineering team to define and implement the SiC and GaN reliability strategy, including establishing look-ahead reliability test plans, overseeing technology and product qualification, and leading JEDEC, AEC-Q101, application-driven, and customer-specific qualification processes.
The HSIO Validation Engineer will own the characterization and qualification of high-speed I/Os—such as PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, and Ethernet—on brand-new silicon serving datacenter, AI, and client markets.
Responsibilities
Own end-to-end characterization and validation of high-speed IO — PCIe, NVLink, NVLink-C2C, UCIe, USB, UFS, Ethernet — from silicon die through package and board, on NVIDIA GPUs, CPUs, and SoCs.
Develop and execute validation test plans for silicon and SoC-level HSIO features — bring-up, corner qualification, stress, productization, and structured DOE across PVT, board, cable/connector, thermal, and firmware variables.
Drive power characterization and optimization across IO interconnects under workload-representative stimuli.
Drive systematic root-cause analysis for complex HSIO bugs — isolating contributions across silicon, package, board, firmware, and driver.
Assess manufacturing and yield implications of HSIO margin distributions.
As Yield Failure Analysis Engineer in Micron NAND Technology Integration (NTI) Singapore department, you will be responsible for providing yield analysis for next-generation Micron products and becoming a domain expert on physical failure analysis methods.
Responsibilities
Perform Failure analysis including conducting electrical characterization, electrical verification to confirm failures, and understanding PFA techniques for de-processing failures
Drive failure analysis initiatives for the yield enhancement team
Create and deliver new methodologies, capabilities, and innovative ways for failure analysis de-processing failures
Participate in global meetings and present results to Product Development and Process Integrations teams
Collaborate with metrology and RDA team to re-define and validate inline detection capability
Design and develop in-house semiconductor test chips, testsites, and test structures to characterize emerging technologies and accelerate technology and customer design enablement.
Compensation
Expected Salary Range
$58,400.00 - $100,800.00
The exact Salary will be determined based on qualifications, experience and location.
Responsibilities
Design and develop in-house test chips, testsites, and test structures to characterize semiconductor technologies and improve understanding of customer design and technology requirements.
Define and implement chip-level and device-level structures that enable electrical measurement, technology characterization, and development learning.
Collaborate with technology development, design enablement, product, test, and manufacturing teams to translate characterization needs into testsite requirements and silicon implementations.
Evaluate and process internal and customer designs through design-to-mask readiness, including layout review and applicable design-rule, verification, and release activities.
Plan and execute electrical characterization and other relevant testing of fabricated test chips to quantify device, interconnect, circuit, and technology behavior.
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Applied Physics, Microelectronics, or a related technical field.
Master’s degree in Electrical Engineering, Computer Engineering, Applied Physics, Microelectronics, or a related field.
Nice to have: Experience designing semiconductor test chips, process-control or characterization structures, or dedicated technology-development testsites
Nice to have: Experience with industry-standard EDA environments and data-analysis tools used for IC design, verification, characterization, and silicon debug
Nice to have: Understanding of CMOS process technology, device physics, parasitic effects, process variation, reliability, and design-technology interaction
