- San Jose, California, United States
- $187K–$268K per year
- 3+ years
Lead ASIC physical design engineering for fullchip floorplan, RTL-to-GDSII implementation, and low‑power design.
Compensation
The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
- Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
- Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
- Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Hands‑on experience with Fullchip clock mesh and Flex‑HTree methods
- RTL‑to‑GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization
- Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements
Requirements
- Bachelor’s Degree in Electrical Engineering
- Master’s Degree in Electrical Engineering
- PhD in Electrical Engineering
- Nice to have: hierarchical design
- Nice to have: timing closure