Own power architecture and modeling for ML accelerator IP, from early concept through tape-out and post-silicon correlation
Build workload-driven power models (energy per op and per byte moved) to evaluate dataflow, memory hierarchy, precision, and sparsity trade-offs before RTL
Deliver cost/benefit analyses that guide architecture decisions
Define power management strategy (clock and power gating, DVFS, retention, power states) and set IP-level power budgets aligned with system battery and thermal targets
Drive hardware-software co-design with ML algorithm, compiler, and firmware teams to optimize power across real use cases
Requirements
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
Master's or Ph.D. in EE, CE, CS, or a related field
In this role, you’ll work to shape the future of AI/ML hardware acceleration by driving cutting-edge TPU (Tensor Processing Unit) technology and developing custom silicon solutions for Google.
Own the planning, creation and delivery of top-level floorplan deliverables and implementation for Silicon SOC projects from concept to working silicon volume.
Resolve structural or physical issues related to the integration of complex ASICs and SOCs and collaborate with teams across Google to develop ideas for high impact Silicon and hardware projects.
Manage all cross-functional interactions related to top-level floorplanning of chip projects.
Develop and improve floorplan implementation methodologies.
Support and execute implementation flows using both industry-standard and specialized internal tools.
Requirements
Bachelor's degree in Electrical Engineering
Computer Engineering
Computer Science
a related field
Nice to have: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science
Lead physical design verification for Microsoft’s cloud infrastructure chips.
Compensation
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Work closely with Physical Design Engineers on LVS, DRC, ERC, Antenna fixes
Drive full chip integration for physical design verification, signoff and Tape‑outs
Collaborate with clock, analog, integration teams on routing, power delivery, block integration
Work with 3pIP and 1pIP teams for SOC‑IP handshake
Work with CAD team, tool vendors, foundry and partners to develop and validate new tools, flows, runsets
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: BS/MS in Electrical or Computer Engineering
Nice to have: 5+ years of experience in semiconductor chip design/SOC physical design
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Technical leadership for ASIC development focusing on fullchip floorplan, RTL-to-GDSII implementation, and physical design.
Compensation
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks
Integration Design Engineer focused on Custom and Digital Design Implementation, specializing in Verilog and System Verilog for programmable logic solutions.
Responsibilities
Custom Design Flow management
Semiconductor principles and transistor-level analysis
Schematic and layout Entry using Cadence Virtuoso
Characterization, performance, and power simulations
Lead technical engagements and drive strategic customer engagements within Cadence’s North America Field Applications Team.
Compensation
The annual salary range for California is $157,500 to $292,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Responsibilities
Lead technical engagements with customers and partners to achieve best-in-class PPA
Guide adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes
Partner with R&D and Product Engineering to influence tool enhancements
Drive complex benchmarks, flow optimizations, and deployment of cutting‑edge methodologies for synthesis, P&R, STA, IR Drop, and power/timing closure
Represent Cadence at industry forums, author technical papers, and deliver keynote presentations
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Hands-on experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
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