- San Jose, California, United States
- Hybrid
- Full-time · Principal
- $129K–$239K per year
- 7+ years
Lead package development activities from early product definition and chip-package co-design through qualification and manufacturing ramp for high-performance semiconductor products.
Compensation
The US salary range for this full-time position is $128,700 to $239,100.
Responsibilities
- Lead early chip-package co-design and package technology selection for new products.
- Develop package solutions across technologies including FCCSP, FCBGA, FCQFN, WLCSP, QFN, and related package platforms.
- Translate product, die, electrical, thermal, mechanical, reliability, manufacturing, and cost requirements into executable package designs.
- Partner with cross-functional teams throughout the product development lifecycle.
- Evaluate package architecture and material options against performance, cost, manufacturability, yield, reliability, and schedule requirements.
Requirements
- Bachelor's degree in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or a related technical discipline
- Master’s degree or Ph.D. in Materials Science, Mechanical Engineering, Electrical Engineering, Chemical Engineering, or a related discipline
- Nice to have: advanced silicon nodes
- Nice to have: complex high-performance package architectures
- Nice to have: Cadence Allegro Package Designer