- San Jose, California, United States
- Full-time
- $148K–$252K per year
- 2+ years
Design and optimize custom test circuit architectures for NAND flash memory, ensuring manufacturability, reliability, and testability across all manufacturing functions.
Compensation
$148,000.00 - $252,000.00 a year
Responsibilities
- Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs
- Interpret product specifications and test requirements; define circuit functionality, interfaces, operating limits, controllability, observability, and validation criteria
- Create, review, and optimize schematics, device sizing, bias structures, sensing and monitoring paths, multiplexers relevant to test circuits
- Analyze circuit testability and robustness to ensure compliance with quality, coverage, manufacturability, power, area, and reliability requirements
- Drive Design for Test (DFT) requirements for custom NAND test circuits, including controllability and observability, test-mode architecture, fault coverage, built-in self-test and diagnostic access
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field