As a Digital Design Engineer, you'll join the team that designs the DSP cores and baseband hardware accelerators behind our next-generation modem products. Working alongside senior designers, you'll take on well-defined blocks and grow into the full design flow, from specification and RTL to synthesis and timing.
Responsibilities
Write and debug RTL (Verilog/SystemVerilog) for blocks within 5G baseband DSP cores and hardware accelerators, under the guidance of senior engineers.
Translate block-level specifications into clean, well-documented, synthesizable designs.
Run lint, synthesis and timing analysis on your blocks, and help resolve the issues they raise.
Support verification engineers in bringing up testbenches, debugging failures and reaching coverage goals.
Take part in design reviews and learn to weigh power, performance and area (PPA) trade-offs.
Als videostagiair bij 433 maak je deel uit van een gepassioneerd team van content creators. Je belangrijkste taak is het editen en vormgeven van video’s voor onze fans over de hele wereld.
Compensation
Een stagevergoeding en een dagelijkse verzorgde lunch op kantoor
Responsibilities
Edit en vormgeven van video’s voor social media platforms
Bedenken van nieuwe concepten en formats
Zorgen dat content snel en sterk op kanalen staat
Requirements
3e- of 4e-jaarsstudent in de richting van een audiovisuele, multimedia of een andere gelijkwaardige opleiding
First in-house Motion Designer & Video Editor responsible for bringing Pogo's products and brand to life through video across B2B marketing and B2C growth teams.
Locations (2)
United States
Canada
Responsibilities
Bring B2B product to life through product demos, launch videos, explainers, and marketing content.
Create original UI animations and motion graphics.
Create high-performing consumer ads by editing UGC, creator footage, and raw assets.
Edit founder, customer, and brand content, including interviews and testimonials.
Own the end-to-end production process from concept development and storyboarding through animation, editing, sound, captions, and final delivery.
Lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs.
Compensation
The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Lead architecture and design of CPU subsystems
Use expertise in all stages of ASIC development from specification and RTL design through post-silicon bring-up
Collaborate closely with SDK, board-support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms
Requirements
Bachelor’s + 8 years of related experience
Master’s + 6 years of related experience
PhD + 3 years of related experience
Nice to have: CPU/SoC subsystem architecture
Nice to have: high-performance networking or data-center SoCs
Independently responsible as Prototype Purchasing contact for assigned seat-complete program builds and associated JIT and Structural Products seat assembly plant(s).
Ensure timely selection of suppliers for all prototype components to meet seat-complete program team milestones.
Responsible for procuring, analyzing and managing of supplier component and tooling costs for the assigned programs.
Establishes a workable bill of material, when applicable, and part delivery for multiple programs with the Program Engineers, Program Manager, and Project Coordinator.
Receives purchase orders requisitions from engineering with description, all pertinent information and CAD data.
Requirements
Bachelor’s degree (or bachelor’s equivalency) in Business Administration or related field or combination of equivalent education and experience.
Lead the development, integration, and productization of high-performance interface solutions for FPGA products.
Responsibilities
Lead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related interface subsystems.
Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.
Drive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
Work with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.
Drive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
Senior Design Engineer – Modeling position develops, validates, and delivers IP behavioral models and related hardware collateral used by internal engineering teams and software-facing customers.
Responsibilities
Develop and maintain IP functional and behavioral models using Verilog, SystemVerilog, and, where applicable, SystemC and C++.
Translate IP specifications, schematics, RTL, and design intent into clear model requirements, implementation plans, and verification objectives.
Perform functional testing, audits, lint and CDC checks, regression testing, and consistency or equivalency checks against approved hardware references and specifications.
Lead or support the generation, audit, validation, and release of timing, power, signal-integrity, configuration, and metadata deliverables used for hardware and software integration.
Investigate and resolve model behavior, hardware-to-software integration, and customer-facing issues across the IP development lifecycle.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field
Stage - Videograaf (feb 2027)New433 · Amsterdam, Netherlands
Motion Designer & Video EditorNewPogo Technologies, Inc. · Remote, US+1 more
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ASIC Design Technical Lead (CPU subsystems)NewCisco · San Jose, US