- Hyderabad, Telangana, India
- Principal
- 8+ years
Principal SRAM Design Engineer responsible for high-performance memory IP and testchip content for advanced semiconductor technologies.
Responsibilities
- Design, develop and verify memory-array subsystems including bitcell arrays, precharge and equalization, sense amplifiers, write drivers, address decoders, wordline drivers, control logic
- Evaluate bitcell and peripheral-circuit stability, performance, leakage, dynamic power, and area across process, voltage, temperature, mismatch, and aging conditions
- Own transistor-level simulation and signoff using Spectre/FineSim, or comparable tools, including PVT corners, Monte Carlo analysis, parasitic-aware post-layout simulation, and waveform/debug reviews
- Partner with layout engineers on floorplanning, bitcell-array composition, matching, critical-net routing, clock and control distribution, parasitic reduction, and layout-dependent effects
- Develop or improve automation for simulation setup, corner execution, results extraction, validation, and regression using Python, Tcl, Perl, SKILL, or similar languages
Requirements
- BS/MS/PhD in Electrical Engineering, Electronics, VLSI, Microelectronics, Computer Engineering, or a related field
- Nice to have: low-power SRAM compilers
- Nice to have: register-file compilers
- Nice to have: bitcell and peripheral circuit stability analysis
- Nice to have: PPA aware design schemes