Referso Jobs

Machine Learning — PhD Intern (Variable Circuit, Place-and-Route, and Layout Representations)

Keysight · Posted Nov 9, 2026

Open

Barcelona, Barcelona, Spain
Internship · Intern

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Machine Learning — PhD Intern (Variable Circuit, Place-and-Route, and Layout Representations)

Keysight · Posted Nov 9, 2026

Open

Barcelona, Barcelona, Spain
Internship · Intern

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R&D IC Design Engineer

Keysight · Posted Nov 5, 2026

Open

Böblingen, Baden-Württemberg, Germany
On-site
Full-time · Mid
3+ years

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As a key contributor in a diverse team, you will design, layout, and validate high performance millimeter-wave ICs powering Keysight’s next generation instruments.

Responsibilities

Design of building block MMIC components in internal and external foundries
Implements full design cycle flow: DRC, LVS, 2.5/3D EM, thermal, characterization
Communicates performance of IC with internal customers via simulations and design reviews
Working closely with internal customers to understand and define critical performance parameters
Matching requirements to advanced semiconductor processes

Requirements

M.S.
Ph.D.
Nice to have: high power in a single MMIC (> +30dBm)
Nice to have: system level analysis
Nice to have: device modelling

Skills

mm-wave IC design advanced semiconductor technologies transistor/diode level design physical layout verification (DRC, LVS)

MCU/SoC System Control Subsystem Development Engineer

Renesas Electronics · Posted Nov 5, 2026

Open

Kodaira, Japan

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Design and develop system control subsystems for microcontrollers and SoCs, covering architecture, logic design, and verification.

Responsibilities

Develop system control functions for chip operation
Design and enhance system architectures for new product families
Cover digital design flow from specification to verification

Skills

logic design functional verification logic synthesis performance verification power consumption verification timing verification analog circuits power management oscillators LSI backend design DFT

Principal Applications Engineer, Transistor-Level Signoff-19643

Synopsys · Posted Nov 4, 2026

Open

Principal
10+ years

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A senior technical role focused on transistor-level power integrity and EM/IR signoff. The role involves owning technical customer relationships, leading signoff work for advanced nodes and 3DIC, mentoring junior engineers, and collaborating with R&D.

Responsibilities

Own technical relationships with assigned customer accounts, serving as the primary technical contact for Totem and Totem-SC engagements, driving adoption, methodology development, and issue resolution.
Lead transistor-level power integrity and EM/IR signoff work across analog, RF, ESD, embedded memory, and high-speed interface designs.
Develop, validate, and optimize customer signoff flows for advanced nodes and 3DIC designs, including scripting in Python, Tcl, Perl, or Shell to automate workflows.
Drive complex technical investigations from initial customer reports through root-cause analysis and resolution, coordinating with R&D and internal teams.
Lead technical evaluations, benchmarks, workshops, and training sessions, partnering with Sales to expand product adoption.

Requirements

Bachelor's in Electrical Engineering
Master's in Electrical Engineering
Nice to have: Totem
Nice to have: Totem-SC
Nice to have: analog/RF

Skills

transistor-level power integrity EM/IR signoff

MMIC Design Engineer

Keysight · Posted Nov 3, 2026

Open

Santa Rosa, California, United States
On-site
Full-time · Entry
$109K–$221K per year
0+ years

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Design, layout, and validate high performance millimeter-wave ICs for Keysight’s next generation instruments.

Compensation

California pay range: MIN $109,170 - MAX $220,550.00

Responsibilities

Design, layout, and validate high performance millimeter-wave ICs
Work closely with internal customers to define performance parameters
Match requirements to advanced semiconductor processes
Execute, characterize, and document final design
Use industry leading tools and collaborate with engineering team

Requirements

M.S., or Ph.D. in Electrical Engineering or closely related field

Skills

mm-wave IC design transistor/diode level design physical layout verification (DRC, LVS)measurement validation mm-wave frequency circuits (mixers, amplifiers, multipliers, filters at >30GHz)

Machine Learning — PhD Intern (Variable Circuit, Place-and-Route, and Layout Representations)

Machine Learning — PhD Intern (Variable Circuit, Place-and-Route, and Layout Representations)

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Requirements

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R&D IC Design Engineer

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Requirements

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MCU/SoC System Control Subsystem Development Engineer

Responsibilities

Skills

Principal Applications Engineer, Transistor-Level Signoff-19643

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Requirements

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MMIC Design Engineer

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Physical layout jobs

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