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1–2 jobs· newest first

Principal FPGA Micro-ArchitectNew
Lattice Semiconductor · San Jose, US
$250KFull-time · Principal
SMTS Silicon Design Engineer
Advanced Micro Devices, Inc · Santa Clara, US

+10K new in the last hour

Principal FPGA Micro-Architect

Lattice Semiconductor · Posted Nov 5, 2026

San Jose, California, United States
Full-time · Principal
$250K per year
15+ years

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We are seeking a Principal FPGA Micro-Architect with deep expertise in programmable logic fabric design and a track record of delivering next-generation FPGA devices from concept to silicon.

Compensation

Base Pay Range 250,000.00. In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.

Responsibilities

Define micro-architecture of core fabric primitives: Programmable Logic Elements, DSP blocks, embedded memory blocks, interconnect routing, configuration memory, carry chains, and clocking structures
Drive fabric PPAU (power, performance, area, and utilization) optimization; evaluate implementation and routing feasibility and drive design trade-offs for modularity and scalability across device generations
Develop SystemC/C++ architectural models to drive performance analysis and evaluate fabric design trade-offs ahead of RTL/schematic availability
Lead advanced low-power fabric design including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching
Drive software primitive definition and implementation strategy, ensuring fabric elements are optimally mapped to CAD tools and customer design flows for maximum usability

Requirements

MS/PhD in Electrical or Computer Engineering
Nice to have: agentic AI methodologies

Skills

FPGA fabric micro-architecture SystemVerilog/Verilog SystemC/C++low-power design silicon validation post-silicon debug SystemC C++SystemVerilog Verilog

Benefits

healthcare
retirement plans
paid time off

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SMTS Silicon Design Engineer

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Santa Clara, California, United States
4+ years

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Design verification engineer for AMD’s CDFX DV team, focusing on DFT IP verification, test plan creation, and debugging regression failures.

Responsibilities

Create and develop IP level test plans
Conduct and participate in test plan reviews
Develop scalable verification components
Generate random-constrained stimulus
Debug regression failures

Requirements

Master's degree

Skills

Design verification on complex CPU/ASIC projects Functional design verification Test bench architecture Tool integration Coverage analysis Power domain management Random constrained testing Debugging regression failures

Post-Silicon debug

Feedback integration

Code coverage closure

Leading a small design verification engineering team

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