Drive verification activities for complex digital designs at the block and system level.
Develop and execute verification plans based on functional and performance specifications.
Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
Develop verification tests, functional coverage, checkers, and other verification components.
Take ownership of verification environments and verification execution for assigned blocks and features.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.