- San Jose, California, United States
- Senior
- $70K–$205K per year
- 8–10 years
Lead complex semiconductor layout design and verification for physical implementation and product outcomes.
Compensation
The annual base salary range for this position, which could be performed in the US, is $70,304-$205,000.*
Responsibilities
- Define and execute highly complex layout architectures, floorplans, device structures, interconnect, power distribution, matching, shielding, extraction, and verification strategies within approved scope.
- Integrate circuit, interface, technology, performance, power, area, reliability, manufacturability, design-rule, and schedule requirements.
- Resolve critical layout, connectivity, parasitic, matching, coupling, electromigration, physical-verification, integration, or tapeout-readiness issues through structured root-cause leadership.
- Evaluate evidence quality, uncertainty, risks, dependencies, waivers, and alternative approaches; communicate decision-ready recommendations.
- Coordinate cross-functional technical decisions and layout closure within approved scope.
Requirements
- Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field
- Nice to have: Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Physics, or a related field
- Nice to have: experience with semiconductor custom, analog, digital, mixed-signal, memory, IO, pad, RF, ASIC, or SoC layout