- Shanghai, China +1 more
Locations (2)
- Shanghai, China
- Beijing, China
Responsibilities
- Verification Planning: Analyze specifications to define verification scope, features, and coverage goals
- Testbench Development: Build and maintain block- and system-level environments using SystemVerilog, UVM, or C++
- Test and Regression: Create test cases, run regressions, and drive functional and coverage closure
- Debug: Investigate failures across RTL, testbench, and system boundaries, and drive them to resolution with the design team
- Auxiliary Verification: Support formal verification, directed testing, and FPGA-based validation
Requirements
- Master's degree
- Nice to have: Python
- Nice to have: Perl
- Nice to have: Tcl
- Nice to have: AI coding assistants