Design, develop, validate, and debug hardware modules and systems for NetApp products.
Compensation
The target salary range for this position is 125,000 to 145,000 USD The salary offered will be determined by the candidate's location, qualifications, experience, and education and may be outside of this range.
Responsibilities
Design, develop, validate, and debug HW modules and systems
Provide technical support to marketing, sales, operations, and design partners
Evaluate product designs for technical feasibility
Diagnose issues within x86 design schematics
Lead small teams or projects
Requirements
Bachelor’s degree in Mechanical Engineering, Hardware Engineering, or a related technical field
Responsible for definition, design, verification and documentation for ASIC and FPGA developments, including architecture, simulation, synthesis, place and route, timing, power utilization, test planning, and vendor evaluation.
Compensation
Combined Salary Range USD $122,785.00 - USD $136,215.00 /Yr.
Responsibilities
Define architecture, system simulation and detailed design approach
Create test and simulation plans
Verify test results and analyze performance
Review vendor capabilities and foundry technologies
Participate in improvement of ASIC/FPGA processes
Requirements
Bachelor’s degree in Electrical or Computer Engineering
Master’s degree in Electrical or Computer Engineering
As a member of the hardware sustaining team, the engineer will participate in the support of hardware platforms throughout the product's life. This includes both root cause analysis of field issues as well as the qualification of 2nd source and EOL parts/components. Opportunities to participate in development and validation of new products are also available.
Compensation
The target salary range for this position is 125,000 to 145,000 USD The salary offered will be determined by the candidate's location, qualifications, experience, and education and may be outside of this range. The range is based on 'On Target Earnings’ (OTE) representing the total potential earnings, which is the sum of the base salary and potential commission earned when performance targets are achieved. Final compensation packages are competitive and in line with industry standards, reflecting a variety of factors, and include a comprehensive benefits package.
Responsibilities
design, development, validation, and debug of HW modules and systems
Provides technical support to marketing, sales, operations, and design partners throughout the life of the product
Requirements
Bachelor’s degree in Mechanical Engineering, Hardware Engineering, or a related technical field
The technical leader will be responsible for System and Silicon debug of AMD EPYC Server & AMD Instinct products. The successful candidate will work as part of the post-silicon validation group; facilitating all aspects of debug and resolution for system level failures working with engineering teams across AMD.
Locations (4)
Seattle, Washington, United States
Austin, Texas, United States
Secaucus, New Jersey, United States
Markham, Ontario, Canada
Responsibilities
Debug issues found during Silicon bring-up, Systems Validation, and production phases of SOC programs
Lead complex debug efforts for internal Silicon findings to identify root cause and resolution
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