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1–2 jobs· newest first

Sr Principal SoC DFT EngineerNew
GlobalFoundries · Bangalore, India
Principal
Staff Engineer Test Technology
Infineon · US
Staff

+10K new in the last hour

Sr Principal SoC DFT Engineer

GlobalFoundries · Posted Nov 9, 2026

Bangalore, Karnataka, India
Principal
10+ years

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AI

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Senior technical authority for complex custom SoC designs, defining DFT strategy and architecture, leading high-impact initiatives, and influencing cross-functional technical direction.

Responsibilities

Define DFT strategy, architecture, methodology, and signoff criteria for complex SoCs and multiple interdependent technical areas.
Lead high-impact DFT initiatives spanning planning, risk management, execution, manufacturing readiness, silicon quality, and test cost.
Architect scalable solutions for scan and ATPG, compression, memory test and repair, logic BIST, test access, boundary scan, IJTAG, and mixed-signal test.
Establish readiness and signoff frameworks, close critical risks, and provide evidence-based recommendations to engineering and program leadership.
Solve critical DFT problems of exceptional complexity and establish reusable approaches across products and teams.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 10+ years of relevant experience; or bachelor’s degree with 15+ years of relevant experience.
Nice to have: advanced DFT methodologies
Nice to have: hierarchical ATPG
Nice to have: streaming scan
Nice to have: logic BIST

Skills

SoC DFT scan ATPG compression memory test repair test clocking boundary scan hierarchical DFT DFT implementation verification signoff silicon lifecycle architecture RTL integration physical implementation pattern generation tapeout silicon bring-up high-volume manufacturing fault models test coverage diagnosis test time manufacturing risk test cost DFT EDA toolchains SNPS Python Tcl Perl Shell

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Staff Engineer Test Technology

Infineon · Posted Nov 4, 2026

United States
Staff
6+ years

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Lead development of production test solutions for Infineon’s AI power management products.

Responsibilities

Develop ATE test package for wafer probe, final test production and product characterization
Document test requirements, test concept, create test plans and develop test methods
Work with design and concept engineers to incorporate DFT features into new products
Participate in firmware development for test, embedded test and data processing
Implement build-in self-test (BIST) features

Requirements

Bachelor's or Master of Science degree in Electrical, Electronics Engineering

Skills

ATE wafer probe final test characterization mixed-signal ICs Advantest V93K Teradyne J750/MicroFlex test hardware

firmware development

data processing

silicon characterization

test platform transfer

new test platforms

test throughput

Cadence Allegro

embedded programming

script languages

signal generators

spectrum analyzers

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