The position has responsibility for product/test engineering for new product development and manufacturing, focusing on semiconductor IC development, manufacturing, fabrication, testing, and packaging.
Compensation
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Responsibilities
Drive product/test engineering for new product development and manufacturing.
Drive pre-Si readiness for power, performance, Thermal and Power delivery (LDOs, Integrated VRs) related tests and features for successful bring up during power on.
Drive Power and Performance tuning during post-Si phase in partnership with platform teams.
Drive ATE test program implementation to optimize for SOC power/TDP.
Work closely with platform/system engineers to drive necessary correlation work to enable such optimizations.
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up, supporting various phases of SoC DFT-related activities for Broadcom APD’s designs.
Compensation
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
Responsibilities
Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Working closely with STA and DI Engineers design closure for test
Generating, Verifying & Debugging Test vectors before tape release
Validating & Debugging Test vectors on ATE during the silicon bring up phase
Integrates product quality and security responsibilities across New Product Introduction (NPI) and Return Material Authorization (RMA) engineering for semi-conductor products, ensuring product readiness, reliability, and outgoing quality.
Responsibilities
Serve as Quality Engineering representative in NPI core teams, ensure reliability, supplier readiness, customer RMA readiness, and product readiness deliverables are met for new product launch.
Work with cross-functional teams (Product Security QRE, Packaging, PTE, Systems, Design, etc.) to make sure lessons-learned and corrective/preventative actions are applied upstream during product development.
Lead technical and business teams to resolve escalated Quality and Security issues in HVM, including factory excursions and non-conforming materials disposition.
Conduct technical evaluations of customer returned devices at system and device levels utilizing tools such as ATE, XRAY, CSAM, IV curve, system level test, and bench leading to a clear path of root cause.
Track actions, schedules and owners to maintain targeted RMA analysis cycle time. Initiate internal corrective actions where applicable.
Requirements
BS in Electrical/Electronics/Computer Engineering
MS in Electrical/Electronics/Computer Engineering
PhD in Computer Science or Electrical/Electronics Engineering
This Staff-level NPI Product Quality/RMA Engineer integrates the full spectrum of Product Quality responsibilities across both New Product Introduction (NPI) and Return Material Authorization (RMA) engineering for semi-conductor, PCIe/Server/Rack for AI DataCenter product Lines.
Responsibilities
Serve as Quality Engineering representative in NPI core teams, ensure reliability, supplier readiness, customer RMA readiness, and product readiness deliverables are met for new product launch.
Work with cross-functional teams (QRE, Packaging, PTE, Systems, Design, etc.) to make sure lessons-learned and corrective/preventative actions are applied upstream during product development.
Lead technical and business teams to resolve escalated Quality issues in HVM, including factory excursions and non-conforming materials disposition.
Conduct technical evaluations of customer returned devices at system and device levels utilizing tools such as ATE, XRAY, CSAM, IV curve, system level test, and bench leading to a clear path of root cause.
Track actions, schedules and owners to maintain targeted RMA analysis cycle time. Initiate internal corrective actions where applicable.
Senior engineer responsible for product qualification testing of electronic power supplies and battery backup systems, supporting NPI and EC processes.
Responsibilities
Develop qualification test strategies for electronic power supplies
Create detailed qualification test plans
Coordinate unit under test samples
Identify test equipment and fixtures
Design automated test systems (ATE)
Requirements
Bachelor’s degree in electrical engineering
Nice to have: Master’s Degree in Electrical Engineering
Planning and executing hardware tests of assemblies and components within projects, writing test specifications and reports, managing testing equipment and defects.
Responsibilities
Planning and executing hardware tests of assemblies and components within projects
Writing hardware test specifications and test execution reports
Preparing and implementing testing work plans
Planning the required testing equipment and tools
Managing hardware defects
Requirements
Engineering degree in Electrical Engineering, Electronics Engineering, Software Engineering, or Technology
The successful candidate will work on DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production.
Compensation
The annual base salary range for this position is USD To USD
The Test Architect / Test Development Engineer is responsible for the development and deployment of next-generation semiconductor test solutions, technologies, and methodologies for SiTime’s precision timing products. The role works across Design Verification (DV), Design for Test (DFT), Product Engineering, and production ATE to accelerate silicon bring-up and improve test development automation.
Compensation
$116,900—$160,710 USD
Responsibilities
Develop and deploy next-generation ATE, Design-to-Test, and pre-silicon test methodologies
Work with Design and DV teams to define Design for Test (DFT) features and improve device testability
Develop test and verification environments integrating simulation, DV, DFT, and ATE
Develop reusable test methods, test IP, software tools, and automation infrastructure
Develop and deploy AI-assisted engineering workflows for test development, code generation, debug, data analysis, documentation, and test automation
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