- San Jose, California, United States
- Senior
- $210K–$280K per year
- 8+ years
Senior/Lead VLSI Design Engineer responsible for architecting and optimizing global circuit areas including custom clocking, low-power design, and power distribution integrity for SambaNova’s AI accelerators.
Compensation
$210,000—$280,000 USD
Responsibilities
- Architect, design, and perform transistor level circuit design and optimization of custom ultra-low-jitter, low-skew chip-level clock distribution networks
- Perform comprehensive signal integrity, power integrity, jitter, skew, and EM/IR analyses across all chip-level clock distribution networks
- Involved in low-power design methodology and power analysis of key components
- Collaborate closely with Physical Design teams on floor-planning, custom routing, shielding strategies, and Clock Tree Synthesis guidelines
- Partner with IP teams to select, evaluate, and integrate custom IO pads, level translators, primary/secondary ESD clamps, and rail protection structures
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or Microelectronics
- Nice to have: MS/Ph.D. in Electrical Engineering
- Nice to have: 10+ years of industry experience
- Nice to have: AI tools
- Nice to have: Python