Referso Jobs

Applications Engineering, Sr Staff Engineer-19681

Synopsys · Posted Nov 6, 2026

Open

Full-time · Senior
12+ years

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Applications Engineering, Sr Staff Engineer-19681

Synopsys · Posted Nov 6, 2026

Open

Full-time · Senior
12+ years

Apply with RefersoAI Apply on careers page

Senior/Lead VLS Engineer - Global Circuits

SambaNova Systems · Posted Nov 5, 2026

Open

San Jose, California, United States
Senior
$210K–$280K per year
8+ years

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Senior/Lead VLSI Design Engineer responsible for architecting and optimizing global circuit areas including custom clocking, low-power design, and power distribution integrity for SambaNova’s AI accelerators.

Compensation

$210,000—$280,000 USD

Responsibilities

Architect, design, and perform transistor level circuit design and optimization of custom ultra-low-jitter, low-skew chip-level clock distribution networks
Perform comprehensive signal integrity, power integrity, jitter, skew, and EM/IR analyses across all chip-level clock distribution networks
Involved in low-power design methodology and power analysis of key components
Collaborate closely with Physical Design teams on floor-planning, custom routing, shielding strategies, and Clock Tree Synthesis guidelines
Partner with IP teams to select, evaluate, and integrate custom IO pads, level translators, primary/secondary ESD clamps, and rail protection structures

Requirements

Bachelor’s or Master’s degree in Electrical Engineering or Microelectronics
Nice to have: MS/Ph.D. in Electrical Engineering
Nice to have: 10+ years of industry experience
Nice to have: AI tools
Nice to have: Python

Skills

custom analog/mixed-signal VLSI design

Staff Engineer, ASIC Analog Design – AI/CAD

Micron Technology · Posted Nov 4, 2026

Open

Minneapolis, Minnesota, United States
Full-time · Mid
$150K–$256K per year
6+ years

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ASIC Analog Design Engineer on Micron’s ASIC design team, focused on supporting the AI and Virtuoso design environment, shaping ASICs used in Micron's tester and controller IP.

Compensation

$150,000.00 - $256,000.00 a year

Responsibilities

Be part of a highly skilled, high-speed PHY design team working on deep sub-micron technology nodes.
Flex between environment maintenance, flow development, and traditional schematic/layout designer roles as required by group needs.
Support enhancements and resolve bugs in the analog environment for both front-end and back-end tools and flows.
Maintain knowledge graph, graphRAG, or other information sources to improve effectiveness of AI agents.
Explore new ways of working to improve efficiency and quality of designs.

Requirements

B.S. in Electrical Engineering
M.S. in Electrical Engineering
Ph.D. in Electrical Engineering
Nice to have: generative AI principles
Nice to have: Virtuoso analog design tools

Skills

ASIC analog design deep sub-micron design high-speed PHY design

Staff Engineer, ASIC Analog Design – AI/CAD

Micron Technology · Posted Nov 4, 2026

Open

Minneapolis, Minnesota, United States
Full-time · Mid
$150K–$256K per year
6+ years

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ASIC Analog Design Engineer on Micron’s ASIC design team, focused on supporting the AI and Virtuoso design environment.

Compensation

$150,000.00 - $256,000.00 a year

Responsibilities

Be part of a highly skilled, high-speed PHY design team working on deep sub-micron technology nodes.
Flex between environment maintenance, flow development, and traditional schematic/layout designer roles as required by group needs.
Support enhancements and resolve bugs in the analog environment for both front-end and back-end tools and flows.
Maintain knowledge graph, graphRAG, or other information sources to improve effectiveness of AI agents.
Explore new ways of working to improve efficiency and quality of designs.

Requirements

B.S. in Electrical Engineering
M.S. in Electrical Engineering
Ph.D. in Electrical Engineering
Nice to have: generative AI principles
Nice to have: Virtuoso analog design tools

Skills

ASIC analog design deep sub-micron technology high-speed PHY design

Layout Design, Staff Engineer- 19592

Synopsys · Posted Oct 30, 2026

Open

Full-time · Staff
5+ years

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Staff Engineer to lead layout development for cutting-edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies, while mentoring juniors and collaborating with cross-functional teams.

Responsibilities

Lead layout development for cutting edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies
Own floorplanning, layout matching, ESD design, latch-up mitigation, and DFM compliance for analog and mixed-signal blocks
Drive layout reviews, quality checks, PERC and EMIR analysis, and release processes that meet both internal standards and customer requirements
Mentor junior layout engineers through hands-on technical leadership, teaching them how to solve real problems in deep submicron design
Collaborate with cross-functional teams including analog designers, verification engineers, and foundry partners to meet project timelines

Requirements

BTech
MTech
Electronics Engineering
VLSI
Nice to have: PHY level customer requirements

Skills

layout design analog mixed-signal PHY IP development

Applications Engineering, Sr Staff Engineer-19681

Applications Engineering, Sr Staff Engineer-19681

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Requirements

Skills

Senior/Lead VLS Engineer - Global Circuits

Compensation

Responsibilities

Requirements

Skills

Staff Engineer, ASIC Analog Design – AI/CAD

Compensation

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Staff Engineer, ASIC Analog Design – AI/CAD

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Requirements

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Layout Design, Staff Engineer- 19592

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PERC jobs

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