- Cupertino, California, United States
- On-site
- $174K–$225K per year
Design Verification Engineer
Compensation
base pay range for this role is between $174,149 - $225,300/yr
Responsibilities
- Work closely with architecture and RTL designers verifying the functionality correctness of the design
- Develop and lead test plans and test environments
- Develop complex tests in assembly, C, or vectors according to test plans
- Develop coverage monitors and analyze coverage to ensure all the test cases in the plans are covered
- Develop checkers or C-based transactor to verify the design
Requirements
- Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or related field