Referso Jobs

Architect - Subsystem Interoperability & AI-Driven Verification

Synopsys · Posted Nov 11, 2026

Open

Bangalore, India
Lead
15+ years

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Architect - Subsystem Interoperability & AI-Driven Verification

Synopsys · Posted Nov 11, 2026

Open

Bangalore, India
Lead
15+ years

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Senior Design Verification Engineer

Advanced Micro Devices, Inc · Posted Nov 12, 2026

Open

Bangalore, Karnataka, India
Full-time · Senior

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An adaptive, self-motivative design verification engineer to join the team, working on verification of complex Analog/Mixed-Signal IPs targeted for integration into AMD SoCs.

Responsibilities

Develop/Maintain tests for functional verification and performance verification at the core level
Build testbench components to support the next generation IP
Maintain or improve current test libraries to support IP level testing
Develop feature-level verification plans and verify IP across RTL, gate-level simulation, and Analog/Mixed-Signal simulation
Develop SystemVerilog/UVM-based testbenches, components, sequences, and verification infrastructure

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Nice to have: Memory PHYs DDRPHY
Nice to have: HBMPHY
Nice to have: GDDRPHY
Nice to have: mixed signal verification

Skills

SystemVerilog UVM SystemVerilog Assertions Functional coverage Code coverage

Lead Engineer Design Verification

Quest Global · Posted Nov 13, 2026

Open

Windsor, Connecticut, United States +1 more
Senior
$172K–$172K per year
2+ years

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Lead Engineer Design Verification

Locations (2)

Windsor, Connecticut, United States
United States

Compensation

Salary $172,210

Responsibilities

Contribute towards bug free first-time pass silicon (Chip), understanding architecture and design of IP to make sure IP use cases are clear and IP is verified correctly with no bugs.
Plan and develop test-benches using standard methodology using different Hardware Description language (HDL).
Run simulation using industry leading tools like Synopsys VCS and Cadence Incisive.
Develop testcases in HDL for exercising scenarios.
Identify and close various functional and code coverage scenarios to achieve 100% code and functional coverage goal.

Requirements

Master’s degree in Electrical Engineering or related field

zTPF Developer

DXC Technology · Posted Nov 12, 2026

Open

Hyderabad, Telangana, India +8 more
2+ years

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zTPF Developer

Locations (9)

Hyderabad, Telangana, India
Bangalore, India
Chennai, Tamil Nadu, India
Kolkata, West Bengal, India
Noida, Uttar Pradesh, India

PCIe Verification Engineer

Broadcom · Posted Nov 11, 2026

Open

Bangalore, India
14+ years

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PCIe Verification Engineer

Responsibilities

Develop UVM based verification testbenches for PCIe subsystems and SoC
Review design specifications and create test plans
Architect testbenches and develop test scenarios
Manage functional and code coverage
Address high-performance design implementation challenges

Requirements

Bachelor's in Electronics/VLSI Engineering
Master's in Electronics/VLSI Engineering

Skills

UVM PCIe Gen5/6/7 PIPE protocols AMBA AXI/AHB/APB design spec reviews testplan creation testbench architectures test scenario development functional coverage

ASIC/FPGA Verification Engineer

Boeing · Posted Nov 10, 2026

Open

El Segundo, California, United States +1 more
On-site
Full-time · Associate
$86K–$171K per year
2+ years

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Design and implement ASIC/FPGA verification environments using UVM & SystemVerilog, develop testbenches, coverage models, and collaborate with cross‑functional teams.

Locations (2)

El Segundo, California, United States
Huntington Beach, California, United States

Compensation

Summary pay range for Associate (Leve 2): $85,850 - $116,150 Summary pay range for Experienced (Level 3) $104,550 - $141,450 Summary pay range for Lead (Level 4): $126,650 - $171.350

Responsibilities

Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
Develop self‑checking and reusable test benches from the ground up.
Create Functional Coverage Models and conduct Code Coverage analysis.
Set up regression tests and collect coverage metrics.
Assist in FPGA‑based prototyping and validation.

Requirements

Bachelor of Science in Engineering (Electrical, Mechanical, or Aeronautical)

Design Verification Engineer

Cystems Logic Inc · Posted Nov 9, 2026

Open

Sunnyvale, California, United States
Contract · Mid

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Develop and execute verification environments for complex semiconductor designs using SystemVerilog and UVM.

Responsibilities

Develop and maintain reusable UVM-based verification environments
Create and implement test plans, test scenarios, and verification strategies
Develop constrained-random and directed test cases using SystemVerilog
Build and maintain UVM components, including agents, drivers, monitors, sequencers, and scoreboards
Develop assertions using SystemVerilog Assertions (SVA)

Skills

UVM SystemVerilog SystemVerilog Assertions (SVA)UVM sequences UVM sequencers UVM drivers UVM monitors UVM agents UVM scoreboards constrained-random verification

CR3210-Baseband硬體工程師

WNC Corporation · Posted Nov 9, 2026

Open

Hsinchu, Taiwan, Taiwan

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Baseband hardware engineer responsible for system integration, validation, and production support in wireless broadband communications.

Responsibilities

Integrate and validate baseband platforms, 5G-RAN transport, RF data, and sync interfaces
Board bring-up through system testing and release verification
Bring-up and design application-layer functions and control-message functionalities
Prototype bring-up and validation of RF/AFE, JESD, SPI, I2C and CAN interfaces
Review schematics and pin assignments and investigate initialization and clock synchronization issues

Skills

Algorithm Analysis Algorithmic Design Application Development Baseband Build Process Circuit Designs Code Coverage Code Refactoring Computer Architecture Debugging Digital Architecture Digital Logics Digital Signal Processing (DSP)Electronic Systems Embedded Operating Systems

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Software Engineering Technical Lead

Trintech · Posted Oct 15, 2026

Open

Bangalore, India
8+ years

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Lead technical design and development of full stack enterprise SaaS applications in a global engineering team.

Responsibilities

Design, develop, test, and maintain full stack enterprise SaaS applications using Java, Spring/Spring Boot, REST APIs, Angular, JavaScript/TypeScript, and SQL Server/Oracle.
Lead technical design, code reviews, implementation approach, and engineering standards within the development team.
Build, test, and deliver complex frameworks, services, UI components, and application features while diagnosing and resolving complex product issues.
Drive clean code, reusable design, SOLID principles, design patterns, secure coding, automated unit testing, and maintainable architecture.
Ensure code quality and compliance using tools and practices such as Sonar, Dependency Track, peer reviews, unit testing, and code coverage guidelines.

Requirements

Bachelor’s degree in Computer Science, Software Engineering, or a related field, or equivalent practical experience.

Skills

Java Spring/Spring Boot RESTful APIs microservices

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