Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
Compensation
$231,500 - $330,000 USD
Responsibilities
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems
Define comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives
Architect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models
Establish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation that improve consistency, quality, reuse, debug efficiency, and predictability across programs
Drive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
Architects, designs, implements, verifies, and optimizes performance and power of GPU cores.
Compensation
$135,700.00 - $203,500.00
Responsibilities
Owning and executing on key independent tasks towards program requirements
Using verbal and written communication skills to convey basic, routine factual information about day-to-day activities to others who are fully knowledgeable in the subject area.
Working within prescribed timeline requirements and resource constraints
Applying independent creative thought to troubleshoot technical problems or deal with novel circumstances.
Research through available resources and engagement with various inter-disciplinary teams
Provide provide technical leadership and execute FPGA verification activities for mission-critical aerospace and defense products, including simulation development, regression execution, hardware integration, and laboratory testing supporting DO-254 compliance.
Responsibilities
Provide hands-on technical leadership for FPGA verification, including verification planning, testbench development, simulation, regression testing, hardware testing, and results analysis.
Develop, maintain, and execute verification environments using VHDL, Verilog, SystemVerilog, Universal Verification Methodology (UVM), and assertion-based verification.
Review requirements for clarity, completeness, and verifiability; develop requirements-based verification procedures and maintain traceability between requirements, tests, and results.
Support DO-254 verification activities, including preparation and review of verification plans, procedures, results, coverage analyses, and supporting lifecycle documentation.
Develop and enhance scalable simulation environments, automated regressions, and scripting infrastructure to improve verification efficiency and repeatability.
Seeking a Senior Digital Design Verification Engineer to develop complex power management SoCs integrating digital control, telemetry, and advanced power functions.
Responsibilities
Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.
Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.
Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions.
Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.
Role focused on pre-silicon verification and post-silicon validation for custom silicon components powering Microsoft's cloud infrastructure.
Compensation
typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.
Responsibilities
Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components.
Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness.
Develop Verification IP (VIP) components to verify home grown designs.
Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments.
Define and implement functional coverage and drive coverage closure.
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