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$154K–$218KHybrid · Full-time · Senior
$164K–$222KHybrid · Full-time · Senior
+10K new in the last hour
Develop RTL (SystemVerilog) modules for ASIC design, debug complex logic and mixed-signal simulations, integrate silicon photonic communication into digital accelerator design, and collaborate across architecture, verification, physical design, photonic, analog, and software teams.
$154,000—$218,000 USD
Lead the development of ASICs for next-generation AI computing architecture, designing RTL modules, debugging mixed-signal simulations, and integrating silicon photonic communication into digital accelerator designs.
$164,000—$222,000 USD