System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers. Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.
Responsibilities
Setup verification environment and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera
Develop and maintain accurate behavioural models for semiconductor devices used in electronic design automation (EDA) tools for circuit simulation.
Work with circuit design and verification teams to ensure that device models integrate seamlessly into simulation tools and deliver reliable simulation results.
Conduct extensive testing and validation of device models against experimental data and simulation results to ensure performance accuracy.
Create comprehensive documentation for device models, including model usage instructions, performance metrics, and limitations.
Stay updated on the latest developments in semiconductor technology and device modeling techniques, and propose enhancements or new modeling approaches to meet future technology demands.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
FPGA Verification Engineer in the Tactical Solutions Strategic Business Unit, responsible for designing, implementing, and testing FPGA verification environments for defense-oriented electronic systems.
Responsibilities
Apply innovative design techniques to create defense-oriented, cutting-edge electronic systems.
Work in a fast-paced team environment on a variety of R&D, proof of concept, and production programs.
Verify FPGA designs, design and implement test benches for both unit level and system level environments, and create reusable verification environments that can be used across multiple projects.
Work in a System Verilog/UVM environment developing tests, testbenches, UVM components, and regressions/testlists.
Be responsible for generating and executing the FPGA Verification Test Plan and FPGA Verification Matrix.
Requirements
BS degree or higher in Engineering or a related technical field
Apply innovative design techniques to create defense-oriented, cutting-edge electronic systems and verify FPGA designs across multiple projects.
Compensation
Minimum $30,000 Sign On Bonus being offered for external hires.
Responsibilities
Apply innovative design techniques to create defense-oriented, cutting-edge electronic systems.
Work in a fast-paced team environment on a variety of R&D, proof of concept, and production programs.
Verify FPGA designs (including SOC architectures utilizing soft-core processors, digital filters, image processing algorithms, and communication interfaces/protocols), design and implement test benches for both unit level and system level environments, and create reusable verification environments that can be used across multiple projects.
Work in a System Verilog/UVM environment developing tests, testbenches, UVM components, and regressions/testlists.
Be responsible for generating and executing the FPGA Verification Test Plan and FPGA Verification Matrix.
Requirements
BS degree or higher in Engineering or a related technical field
Contribute to the design, development, verification, and validation of airborne radar hardware for defense and aerospace applications. Focus on RTL development, FPGA/ASIC design, simulation, and hardware bring-up.
Compensation
The salary range for this role is 75,800 USD - 144,200 USD.
Responsibilities
Design and implement digital hardware blocks using Verilog/SystemVerilog or VHDL
Develop RTL for FPGA and/or ASIC-based systems
Participate in architecture discussions and technical design reviews
Create and execute simulation testbenches for functional verification
Debug RTL, simulation, synthesis, and hardware integration issues
The controls hardware engineer is responsible for designing and implementing electronic controls platform hardware for Nuclear Power Plants.
Compensation
the pay range for this position is between $72,000.00 and $108,000.00. The Company pays a geographic differential of 110%, 120% or 130% of salary in certain areas.
Responsibilities
Creating a design from requirements / helping define requirements where necessary.
Design activities include schematic design, component selection, PCB layout, performing simulation/module testing, and integration testing of the design.
Documenting designs by creating Design Specifications and writing test reports.
Engage customers to define scope, review results, and discuss technical risks.
Work with the technical leader to establish an effective work plan, including time estimates, schedule estimates, requirements, and work processes.
Requirements
Bachelor's Degree in electrical, computer, software, mechatronics, or similar engineering
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