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Physical Design Technical Lead, ASIC, TPU

Google · Posted Nov 4, 2026

Sunnyvale, California, United States
On-site
Full-time · Manager
$192K–$278K per year
10+ years

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Lead the physical design implementation and strategy for high-performance silicon, managing end-to-end execution from RTL to GDSII and driving cross-functional collaboration.

Compensation

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

Responsibilities

Lead the physical design implementation and strategy for high-performance silicon
Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity
Partner with internal teams to achieve optimal power, performance, and area (PPA) results
Collaborate with external EDA and IP vendors to improve flows and methodologies
Drive execution schedules, resource planning, and risk mitigation for your area of ownership

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: Master's degree
Nice to have: PhD

Skills

Python Tcl Perl Cadence Innovus Synopsys DP

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